The present invention relates to the field of linewidth measurement; more specifically, it relates to a semiconductor damascene resistor and a method of forming and measuring the width of the resistor.
In the fabrication of semiconductor structures, the increasing density of devices (transistors, diodes, resistors and capacitors), including the isolation and interconnect structures between devices, has resulted in the devices, isolation, and interconnects becoming increasingly smaller. This, in turn, has produced the need for high-resolution photolithography. Devices utilizing sub-micron linewidths are now routinely fabricated.
Accurate measurement of sub-micron linewidths to characterize the photolithography process is difficult. Linewidths have long since passed the practical optical linewidth measurement limit. Scanning electron microscopy (SEM) measurement is not always satisfactory because of charging effects and because an SEM measures linewidths over only a portion of an entire line. Further, this technique is slow, especially when there is a need to take hundreds of measurements across a single die or thousands across a wafer.
A faster technique is to measure the linewidth electrically. In electrical linewidth measurement the sheet resistance of a conductive material is determined using a test structure, then a known current is passed along second test structure having a line fabricated from the same material. If the line is of known length and thickness, then the linewidth can be calculated from the sheet resistance and the voltage drop along the known length of line. Linewidth measurement of a line formed by subtractive means is well known. To measure a damascene line is more challenging. In a damascene process, a conductive line is formed by etching a trench in an insulator, depositing a layer of conductive material on the top surface of the insulator of a thickness sufficient to fill the trench and then chemical-mechanical-polishing (CMP) the excess conductive material until the top surface of the insulator is exposed again.
FIG. 1 is a cross-section view through a conductive damascene line, illustrating an ideal cross-sectional profile. In FIG. 1, an insulator 100 is formed on top of a substrate 105. Formed in insulator 100 is a damascene conductor 110. Damascene conductor 110 has sidewalls 115, a bottom 120 and a top surface 125. Top surface 125 is co-planar with a top surface 130 of insulator 100. In the idealized structure, the cross-section of conductor 110 is a perfect rectangle. Particularly, sidewalls 115 are perpendicular to top surface 125, the top surface is perfectly flat and co-planar with top surface 130 of insulator 100. Damascene conductor 110 is xe2x80x9cWxe2x80x9d wide by xe2x80x9cTxe2x80x9d thick, where xe2x80x9cTxe2x80x9d is a function only of the depth of the trench after CMP. The resistance R of damascene conductor 110 is given by the formula:
R=xcfx81L/WTxe2x80x83xe2x80x83(1)
where xcfx81 is the resistivity of damascene conductor 110 and L is the length (into the plane of the drawing sheet) of the damascene conductor. Electrical linewidth measurement relies on L and T being accurately known and xcfx81 and R being accurately measured.
However, because this linewidth measurement technique assumes the thickness of lines of the same linewidth do not vary from line to line, the technique is not accurate when sub-micron damascene structures need to be measured because the thickness does vary due to the nature of the damascene fabrication process. The CMP process is not uniform all over the die or wafer. Depending upon line density and linewidth, some lines will be dished, some lines will be eroded and some will be ideal, as in FIG. 1. Worse, lines of the same width may exhibit different amounts of dishing and erosion depending on the local line density.
FIG. 2A a cross-section view through a conductive damascene line illustrating the effect of dishing on the cross-sectional profile of FIG. 1. In FIG. 2A, top surface 125A of conductor 110 is concave instead of flat. The true cross-sectional area of conductor 110 is now a function of the depth of the trench after CMP and of the dishing profile. Dishing is caused by localized differences in pressure caused by localized differences in area ratio of harder line fill material to softer insulating layer material. Obviously, if test structure line profiles vary from ideal to different degrees of dished across the die or wafer, the measurement will not accurately reflect a true linewidth or a true linewidth variation across the die or wafer because the thickness term in equation (1) is no longer accurately known.
FIG. 2B is a cross-section view through a conductive damascene line illustrating the effect of erosion on the cross-sectional profile of FIG. 1. In FIG. 2B, top surface 125B of conductor 110 is recessed a distance xe2x80x9cDxe2x80x9d from top surface 130 of insulator 100. The true thickness of conductor 110 is now a function of the depth of the trench after CMP and of the depth xe2x80x9cDxe2x80x9d of erosion. Erosion is caused by localized differences in pressure caused by localized differences in the number of line edges resulting in faster insulator layer removal in areas having more edges. Again, if test structure line profiles vary from ideal to different degrees of erosion across the die or wafer, the measurement will not accurately reflect a true linewidth or a true linewidth variation across the die or wafer because the thickness term in equation (1) is no longer accurately known.
It would be desirable to provide an electrical linewidth measurement structure and method, not affected by thickness variation, especially those variations caused by the CMP process.
A first aspect of the present invention is a linewidth measurement structure for determining linewidths of damascened metal lines formed in an insulator comprising: a damascene polysilicon line formed in the insulator, the polysilicon line having a doped region having a predetermined resistivity.
A second aspect of the present invention is A method of fabricating a linewidth measurement structure for determining linewidths of damascened metal lines formed in an insulator comprising: forming a trench in the insulator; filling the trench with polysilicon; planarizing the polysilicon to form a polysilicon line; and ion implanting a dopant species and annealing to form within the polysilicon line a doped region having a predetermined resistivity.
A third aspect of the present invention is a method of characterizing the photolithographic process for forming a damascened metal line in an insulating layer of a semiconductor device comprising: forming a trench in the insulating layer using the photolithographic process for forming damascened metal lines; filling and planarizing the trench with polysilicon to form a polysilicon line; forming a doped region in the polysilicon region, the doped region having a predetermined resistivity greater than a resistivity of the material of the damascened metal line; and measuring the effective width of the trench by measuring the resistance of the polysilicon line.
A fourth aspect of the present invention is a resistor, comprising: a damascened polysilicon line formed in a first insulator, the polysilicon line having a first region having a first dopant concentration and a second region having a second dopant concentration, the first dopant concentration being greater than the second dopant concentration; a second insulator formed on a top surface of the first insulator; a first via formed in the second insulator, the first via electrically contacting the first region at a first end of the polysilicon line; and a second via formed in the second insulator, the second via electrically contacting the first region at a second end of the polysilicon line.
A method of fabricating a resistor, comprising: forming a damascened polysilicon line in a first insulator, the polysilicon line having a first region having a first dopant concentration and a second region having a second dopant concentration, the first dopant concentration being greater than the second dopant concentration; forming a second insulator a top surface of the first insulator; forming a first via formed in the second insulator, the first via electrically contacting the first region at a first end of the polysilicon line; and forming a second via formed in the second insulator, the second via electrically contacting the first region at a second end of the polysilicon line.